Tilera tips veil on 100-core processor
In a presentation at the Linley Tech Processor Conference, fabless chip vendor Tilera Corp. has detailed its third generation of multicore processors, headed up by an SoC with 100 64-bit cores. They are targeted at applications such as cloud computing, digital video transcoding, wireless infrastructure, and advanced networking. As with previous Tilera products, the architecture of the Tile-Gx devices is based on a mesh of tiled 64-bit RISC processors, with the cores interconnected by Tilera's proprietary iMesh on-chip network.
Bob Doud, director of marketing at Tilera, said the company's Tile-Gx product line would offer performance increases of two to eight fold compared to the company's current TilePro family. Tile-Gx devices with 16 and 32 cores are expected to be sampling by the end of this year, with 64- and 100-core versions following in mid-2011. The 100-core Tile-Gx100 will feature clock speeds of 1 to 1.5 GHz, a total of 32 MB of cache, and a peak memory bandwidth of 546 GB/s.
According to Doud, the devices will support a broad range of high-speed interfaces, including XAUI, Double XAUi, SGMII, Interlaken, PCI Express and StreamIO. The devices will also feature several co-processing engines, including Tilera's proprietary Multicore iMesh Coprocessing Accelerator (MiCA). Tilera's tile architecture emphasizes modular design and power efficiency and is, according to Doud, highly scalable to a large number of cores, which is a significant advantage as chip vendors continue to increase the number of cores available on SoC devices.
Image: Tilera
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Bob Doud, director of marketing at Tilera, said the company's Tile-Gx product line would offer performance increases of two to eight fold compared to the company's current TilePro family. Tile-Gx devices with 16 and 32 cores are expected to be sampling by the end of this year, with 64- and 100-core versions following in mid-2011. The 100-core Tile-Gx100 will feature clock speeds of 1 to 1.5 GHz, a total of 32 MB of cache, and a peak memory bandwidth of 546 GB/s.
According to Doud, the devices will support a broad range of high-speed interfaces, including XAUI, Double XAUi, SGMII, Interlaken, PCI Express and StreamIO. The devices will also feature several co-processing engines, including Tilera's proprietary Multicore iMesh Coprocessing Accelerator (MiCA). Tilera's tile architecture emphasizes modular design and power efficiency and is, according to Doud, highly scalable to a large number of cores, which is a significant advantage as chip vendors continue to increase the number of cores available on SoC devices.
Image: Tilera
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